12
12.4.6 Typical CSIO Receive Operation
The following shows a typical receive operation in CSIO mode.
<CSIO on receive side>
Receive clock
(SCLKI)
Receive enable bit
RXD
Receive status bit
Receive-finished bit
SIO receive interrupt
(Note 1)
(When receive-finished
interrupt is selected)
(When receive error
interrupt is selected)
Note 1 : Change of the Interrupt Controller "SIO Receive Interrupt Control Register" interrupt request bit
Note 2 : When receive-finished interrupt is enabled (DMA transfer can also be requested at the same
timing)
Note 3 : The Interrupt Controller IVECT register is read or "SIO Receive Interrupt Control Register"
interrupt request bit cleared
Figure 12.4.3 Example of CSIO Reception (When Received Normally)
<CSIO on receive side>
SCLKO
RXD
Internal clock selected
Set
Set by a write to
transmit buffer
: Processing by software
12.4 Receive Operation in CSIO Mode
<CSIO on transmit side>
SCLKI
TXD
External clock selected
D7
D6
D5
D4
D3
Receive-finished interrupt
No interrupt request
: Interrupt generation
12-41
SERIAL I/O
Clock stopped
Cleared
D2
D1
D0
Automatically
cleared for each
receive operation
performed
Read from receive buffer
(Note 2)
Interrupt request accepted
(Note 3)
Ver.0.10