Dma Channel Control Register - Mitsubishi Electric M32R Series User Manual

9

9.2.1 DMA Channel Control Register

DMA0 Channel Control Register (DM0CNT)
D0
MDSEL0 TREQF0
D Bit Name
0 MDSEL0
(Selects DMA0 transfer mode)
1 TREQF0
(DMA0 transfer request flag)
2, 3 REQSL0
(Selects cause of DMA0 request)
4 TENL0
(Enables DMA0 transfer)
5 TSZSL0
(Selects DMA0 transfer size)
6 SADSL0
(Selects DMA0 source address direction) 1 : Incremental
7 DADSL0
(Selects DMA0 destination
address direction)
W = : Only writing a 0 is effective; when you write a 1, the previous value is retained.
1 2 3
REQSL0
Function
0 : Normal mode
1 : Ring buffer mode
0 : Not requested
1 : Requested
00 : Software start or one DMA2 transfer completed
01 : A-D0 conversion completed
10 : MJT (TIO8_udf)
11 : MJT (input event bus 2)
0 : Disables transfer
1 : Enables transfer
0 : 16 bits
1 : 8 bits
0 : Fixed
0 : Fixed
1 : Incremental
9-6
9.2 DMAC Related Registers
<Address: H'0080 0410>
4 5 6
TENL0 TSZSL0 SADSL0
DMAC
D7
DADSL0
<When reset : H'00>
R W
Ver.0.10