Sio Interrupt Related Registers - Mitsubishi Electric M32R Series User Manual

12

12.2.1 SIO Interrupt Related Registers

(1) Selecting the cause of interrupt
Interrupt signals sent from each SIO to the ICU (Interrupt Controller) are broadly classified into
transmit interrupts and receive interrupts. Transmit interrupts are generated when the transmit
buffer is empty. Receive interrupts are either receive-finished interrupts or receive error
interrupts as selected by the Cause of Receive Interrupt Select Register (SI03SEL, SI45SEL).
Note 1 : No interrupt signals are generated unless interrupts are enabled by the SIO Interrupt
Mask Register after enabling the TEN (transmit enable) bit or REN (receive enable) bit
for the corresponding SIO.
Note 2 : SIO2 and SIO3 together comprise one interrupt group, so do SIO4 and SIO5.
(2) Precautions on using transmit interrupts
Transmit interrupts are generated when the corresponding TEN (transmit enable) bit is enabled
while the SIO Interrupt Mask Register is set to enable interrupts.
(3) About DMA transfer requests from SIO
Each SIO can generate a transmit DMA transfer and a receive-finished DMA transfer request.
These DMA transfer requests can be generated by enabling each SIO's corresponding TEN
(transmit enable) bit or REN (receive enable) bit. When using DMA transfers to communicate
with external devices, be sure to set the DMAC before enabling the TEN or REN bits. When a
receive error occurs, no receive-finished DMA transfer requests are generated.
• Transmit DMA transfer request
Generated when the transmit buffer is empty and the TEN bit is enabled.
TEN
(transmit enable bit)
TBE
(transmit buffer
empty bit)
Transmit DMA
transfer request
Figure 12.2.2 Transmit DMA Transfer Request
12.2 Serial I/O Related Registers
12-7
SERIAL I/O
Ver.0.10