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8
8.4 Port Peripheral Circuits
Figures 8.4.1 through 8.4.4 show the peripheral circuit diagrams of the input/output ports described
in the preceding pages.
P00 - P07 (DB0-DB7)
P10 - P17 (DB8-DB15)
P20 - P27 (A23-A30)
P30 - P37 (A15-A22)
___
___
P41 (BLW / BLE)
___
___
P42 (BHW / BHE)
__
P43 (RD)
___
P44 (CS0)
___
P45 (CS1)
P46 - P47 (A13-A14)
P61 - P63
P224 - P225 (A11-A12)
P222 - P223
Note 1: Ports P00-P07, P10-P17, P20-P27, P30-P37, P41-P47, and P224-P225 when operating in
extended external mode or processor mode, function as external bus interface control signals,
but their functional description in this block diagram is omitted.
_____
P67 (ADTRG)
P75 (RTDRXD)
P77 (RTDCLK)
P83 (RXD0)
P86 (RXD1)
P124 - P127 (TCLK0-TCLK3)
P130 - P137 (TIN16-TIN23)
P140 - P147 (TIN8-TIN15)
P150 - P157 (TIN0-TIN7)
P172, P173 (TIN24, TIN25)
P175 (RXD2)
P177 (RXD3)
P190 - P197 (TIN26-TIN33)
P201 (RXD4)
P203 (RXD5)
Note 2:
denotes pins.
Figure 8.4.1 Port Peripheral Circuit Diagram (1)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
Direction
Port output
Data bus
(DB0 - DB15)
Direction
Port output
Data bus
(DB0 - DB15)
Operation
mode register
Peripheral
function input
8-31
8.4 Port Peripheral Circuits
register
latch
Input function
enable
register
latch
Input function
enable
Ver.0.10
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