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5
5.3.2 Interrupt Mask Register
Interrupt Mask Register (IMASK)
D0
D
Bit Name
0 – 4
No functions assigned
5– 7
IMASK (Interrupt mask)
The Interrupt Mask Register (IMASK) is used to finally determine whether an interrupt request
can be accepted after comparing its priority with the priority levels that have been set for each
interrupt source (by setting the Interrupt Control Register ILEVEL bits). When the Interrupt Vector
Register (IVECT) described above is read out, a new mask value (NEW_IMASK) is set in this
IMASK register.
When any value is written to the IMASK register, operations (1) to (2) below are automatically
performed in hardware:
(1) The interrupt request (EI) to the CPU core is cleared.
(2) The ICU's internal sequencer is activated to start internal processing (interrupt priority
resolution).
Note that the Interrupt Mask Register (IMASK) can only be read out by the EIT handler (PSW
register IE bit being disabled).
1
2
3
Function
000 : Maskable interrupts are disabled
001 : Level 0 interrupts can be accepted
010 : Level 0-1 interrupts can be accepted
011 : Level 0-2 interrupts can be accepted
100 : Level 0-3 interrupts can be accepted
101 : Level 0-4 interrupts can be accepted
110 : Level 0-5 interrupts can be accepted
111 : Level 0-6 interrupts can be accepted
CAUTION
5-8
INTERRUPT CONTROLLER (ICU)
5.3 ICU-Related Registers
<Address:H'0080 0004>
4
5
6
IMASK
D7
<When reset: H''07>
R
W
0
–
Ver.0.10
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