Description Of Interrupt Operation; Acceptance Of Internal Peripheral I/O Interrupts - Mitsubishi Electric M32R Series User Manual

5

5.5 Description of Interrupt Operation

5.5.1 Acceptance of Internal Peripheral I/O Interrupts

An interrupt from any internal peripheral I/O is checked to see whether or not to accept by
comparing its ILEVEL value set by the Interrupt Control Register and the IMASK value of the
Interrupt Mask Register. If its priority is higher than the IMASK value, the interrupt is accepted.
However, when multiple interrupt requests occur simultaneously, the interrupt controller resolves
priority between these interrupt requests following the procedure described below.
The ILEVEL values set by the Interrupt Control Register for each interrupt peripheral I/O are
compared with each other.
If the ILEVEL values are the same, they are resolved according to the predetermined
hardware priority.
The ILEVEL value is compared with IMASK value.
When multiple interrupt requests occur simultaneously, the interrupt controller first compares their
priority levels set by each Interrupt Control Register's ILEVEL bit to select an interrupt request
which has the highest priority. If the interrupt requests have the same LEVEL value, they are
resolved according to the hardware-fixed priority.
The interrupt request thus selected has its ILEVEL value compared with IMASK value and if its
priority is higher than the IMASK value, the interrupt controller sends an EI request to the CPU.
Interrupt requests may be masked by setting the Interrupt Mask Register and the Interrupt Control
Register's ILEVEL bit (level 7 = disabled) provided for each internal peripheral I/O and the PSW
register IE bit.
(ILEVEL settings)
MJT Output Interrupt 4
MJT Output Interrupt 3
MJT Output Interrupt 2
MJT Output Interrupt 1
DMA0-4 Interrupt
A-D0 Converter Interrupt
Figure 5.5.1 Example of Priority Resolution When Accepting Interrupt
1
Resolve priority
Interrupt
according to
requested
interrupt priority
or not
levels (ILEVEL)
Level 3
Requested
Level 4
Requested
Level 5
Requested
Level 3
Requested
Level 1
Not requested
Level 3
Requested
5-17
INTERRUPT CONTROLLER (ICU)
5.5 Description of Interrupt Operation
2
Resolve priority
according to
hardware priority
Level 3
Hardware-fixed
priority
Level 3
Level 3
3
Accept interrupt if
Compare with
PSW register IE bit
IMASK value
= 1
Can be accepted when
IMASK = 4-7
Ver.0.10