Video Timing - Xilinx ML40 Series User Manual

Chapter 8: PLB TFT LCD Controller
The PLB interface logic has the ability to skip reading a line of data if it fails to finish
reading data from a previous line. This prevents temporary shortages of available PLB
bandwidth from causing the PLB TFT controller from losing synchronization between the
PLB and TFT interface logic. Note that extreme shortages of available bandwidth for the
PLB TFT controller can cause the screen to appear "unstable" as stale lines of video data are
displayed on the screen.
A DCR interface allows software to change the base address of video memory to be read
from. This allows frames of video to be drawn in other memory locations without being
seen on the display. The software can then change the video memory base address to
display a different frame when it is ready. The DCR interface also allows the display to be
rotated by 180 degrees or turned off. When the display is turned off a black screen is output
while the PLB interface stops requesting data.

Video Timing

The diagrams in
the PLB TFT LCD Controller.
76
Figure 8-2 through
thp
Hsync
th = 800 TFT Clocks (Horizontal)
thp = 96 TFT Clocks
Figure 8-2: Hsync and TFT Clock
Hsync
thp
CLK
1 2
DE
R0 to R5
G0 to G5
B0 to B5
Invalid
thp = 96 TFT Clocks
thb = 48 TFT Clocks
DE = 640 TFT Clocks
thf = 16 TFT Clocks
www.xilinx.com
Figure 8-5 describe the timing of video signals from
th
1CLK
thb 640CLK (Fixed)
D (0,Y) D (1,Y)
Figure 8-3: Horizontal Data
ML40x EDK Processor Reference Design
UG082_08_02_050406
thf
1
D (639,Y) Invalid
UG082_08_03_050406
UG082 (v5.0) June 30, 2006
R