Conclusion - Xilinx ML40 Series User Manual

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Conclusion

Using the IPIF with a small amount of logic makes it very easy to create CoreConnect

devices with little knowledge of the buses used. For complex buses such as PLB, this saves

the designer time and helps to ensure IP functions correctly, since the IPIF provides a pre-

verified design to connect to. The GPIO design is just one example of how IPIF can be used.

More examples of IPIF designs are provided within many of the other IP devices in the

reference systems. The designer who wants to learn about IPIF should study the sample

source code for some of these IPIF-based designs in context with simulation to gain

experience with IPIF.

The IPIF used in the ML40x Embedded Processor Reference System currently supports

only the SRAM module. Additional IPIF modules are available through EDK that support

many parameterizeable features. Refer to the IPIF chapter of the Processor IP Reference

Guide located in <EDK Install Directory>/doc/proc_ip_ref_guide.pdf.

Note:

to an earlier version of the specification. Please refer to the IPIF chapter of the Processor IP

Reference Guide (located in <EDK Install Directory>/doc/proc_ip_ref_guide.pdf) for the latest

information and documentation on IPIF cores. New designs should use these IPIF modules, available

through EDK. For reference, the earlier version of the IPIF spec is available in Chapter 6 of Xilinx

UG057:

ML40x EDK Processor Reference Design

UG082 (v5.0) June 30, 2006

The Hardware Reference IP in the following chapters are built using IPIF modules conforming

ML300 EDK Reference Design User

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Guide.

Conclusion

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