Memory Map - Xilinx ML40 Series User Manual

Chapter 2: ML40x Embedded Processor Reference System

Memory Map

This section diagrams the system memory map for the ML40x Embedded Processor
Reference System. It also documents the location of the DCR devices as mapped by the
OPB to DCR Bridge. The memory map shown in
the system devices as defined in the system.mhs file.
Table 2-2: Memory Maps
PLB Device Memory Map (MicroBlaze)
Device
DDR SDRAM
DDR SDRAM Shadow Memory
PLB Device Memory Map (PPC405)
Device
DDR SDRAM
DDR SDRAM Shadow Memory
PLB to OPB Bridge
BRAM
OPB Device Memory Map
Device
LMB BRAM
OPB to PLB Bridge
OPB EMC (ZBT SRAM)
OPB EMC (Flash)
Ethernet
Dual GPIO
Dual GPIO (Expansion Header)
GPIO (Character LCD)
UART1
OPB EMC (USB)
AC97 Sound
IIC Controller
PS/2 (Dual)
System ACE MPU
OPB to DCR Bridge
OPB INTC
OPB MDM
Memory-Mapped DCR Device Map
Device
TFT VGA Controller
28
Address
Max Min Size
13FFFFFF 10000000 64 MB
Shadow memory allows video memory to be accessed as an uncached
1FFFFFFF 14000000
192 MB
region. Shadow Memory contains three copies of DDR memory.
Address
Max Min Size
03FFFFFF 00000000 64 MB
Shadow memory allows video memory to be accessed as an uncached
0FFFFFFF 04000000 192 MB
region. Shadow Memory contains three copies of DDR memory.
3FFFFFFF 20000000 PPC405 systems only
256 MB
7FFFFFFF 60000000 256 MB PPC405 systems only
DFFFFFFF 80000000
768 MB PPC405 systems only
FFFFFFFF FFFF0000
64 KB
Address
Max Min Size
0000FFFF 00000000 64 KB MicroBlaze systems only
1FFFFFFF 10000000 256 MB
MicroBlaze systems only
200FFFFF 20000000
1 MB
287FFFFF 28000000 8 MB
60003FFF 60000000
16 KB
900001FF 90000000 512 B
900011FF 90001000
512 B
900021FF 90002000 512 B
A0001FFF A0000000 8 KB
A50000FF A5000000 256 B
A60000FF A6000000
256 B
A80001FF A8000000 512 B
PPC405 systems only
A9001FFF A9000000
8 KB
CF0001FF CF000000 512 B
D0000FFF D0000000 4 KB mem addr = DCR addr x 4
D1000FDF D1000FC0 32 B
FFFE80FF FFFE8000 256 B
MicroBlaze systems only
Address
Max Min Size (DCR Addr Range)
D0000207 D0000200 8 B TFT Control Regs (0x080- 0x081)
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Table 2-2 reflects the default location of
Comment
Comment
Comment
Comment
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
R
UG082_02_04_050406