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Table 6-4: Generics (Parameters)
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
Name
C_OPB_AWIDTH
C_OPB_DWIDTH
C_BASEADDR
C_HIGHADDR
C_PLAYBACK
C_RECORD
C_PLAY_INTR_LEVEL
C_REC_INTR_LEVEL
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Default
32
Address bus width of OPB. Should be set to 32.
32
Data bus width of OPB. Should be set to 32.
N/A
Base Address of AC97 Sound Controller. Should be
set to 256-byte (or higher power of 2) boundary.
N/A
End Address of AC97 Sound Controller. Should be
set to (Base Address + 0xFF) or higher. Total memory
space from C_BASEADDR to C_HIGHADDR must
be power of 2.
1
Playback Enable. Set to 1 to allow playback. Set to 0
to remove playback logic.
1
Record Enable. Set to 1 to allow record. Set to 0 to
remove record logic.
2
Sets playback FIFO fullness threshold at which
interrupt is generated:
0 = No Interrupt
1 = empty
2 = halfempty Num Words <= 7
3 = halffull
4 = full
3
Sets record FIFO fullness threshold at which
interrupt is generated:
0 = No Interrupt
1 = empty
2 = halfempty Num Words <= 7
3 = halffull
4 = full
Module Port Interface
Description
Num Words = 0
Num Words >= 8
Num Words = 16
Num Words = 0
Num Words >= 8
Num Words = 16
55
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