Sram Protocol Overview Of Ipif - Xilinx ML40 Series User Manual

Chapter 5: Using IPIF to Build IP

SRAM Protocol Overview of IPIF

Figure 5-1
interface. The IPIF simplifies the design by providing a PLB or OPB interface and
condensing it down to a small set of easily understood signals.
All interface signals with the IPIF are synchronous to rising clock edges. The IPIF takes the
clock from the OPB or PLB bus interface and passes it to the IP, causing the IP to use the
same global clock as the bus it is connected to. The SRAM interface protocol used by the
IPIF can be described by observing a write and read transaction.
46
diagrams the connections between the IPIF and the user IP for SRAM protocol
Bus2IP_Clk
Bus2IP_Addr[m:0]
Bus2IP_Data[0:n]
IP2Bus_Data[0:n]
Bus2IP_BE[0:b]
Bus2IP_SRAM_CE
IP Slave
Peripheral SRAM
Bus2IP_WrReq
Module
IP2Bus_WrAck
Bus2IP_RdReq
IP2Bus_RdAck
IP2Bus_Retry
IP2Bus_Error
IP2Bus_ToutSup
Bus2IP_Reset
IP2Bus_Intr[0:i]
Figure 5-1: IPIF SRAM Module Interface
www.xilinx.com
Bus
IPIF Slave
SRAM Module
Note: Supports
both with and
without DMA
UG082_05_01_050406
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
R