On-Chip Peripheral Bus (Opb) - Xilinx ML40 Series User Manual

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On-Chip Peripheral Bus (OPB)

The OPB connects lower-performance peripheral devices to the system. The OPB has a less
complex architecture, simplifying peripheral development. OPB and PLB devices can
communicate by way of an OPB-to-PLB Bridge or an PLB-to-OPB Bridge.
The OPB devices in the reference system include:
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•
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In general, all OPB devices are optimized around the FPGA architecture and make use of
pipelining to improve maximum clock frequencies and reduce logic utilization. Refer to
the accompanying documentation for each device for more information about its design.
The OPB devices in the reference design make use of Intellectual Property InterFace (IPIF)
modules to further simplify IP development. The IPIF converts the OPB protocol into
common interfaces, such as an SRAM protocol or a control register interface. IPIF modules
also provide support for DMA and interrupt functionality. IPIF modules simplify software
development because the IPIF framework has many common features. Refer to
"Using IPIF to Build IP"
The IPIF is designed mainly to support a wide variety of common interfaces, but might not
be the optimal solution in all cases. Where additional performance or functionality is
required, the user can develop a custom OPB interface. The IPIF protocols can also be
extended to support other bus standards, such as PLB. This allows the backend interface to
the IP to remain the same while the bus interface logic in the IPIF is changed. This provides
an efficient means for supporting different bus standards with the same IP device.
The OPB specification supports masters and slaves of up to 64 bits with a dynamic bus sizing
capability that allows OPB masters and slaves of different sizes to communicate with each
other. The ML40x Embedded Processor Reference System uses a subset of the OPB
specification that supports only 32-bit byte enable masters and slaves. Legacy devices
utilizing 8- or 16-bit interfaces or those that require dynamic bus sizing functionality are
not directly supported. It is recommended that all new OPB peripherals support
byte-enable operations for better performance and reduced logic utilization.
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
OPB Masters
♦
Ethernet Controller (DMA Engine, if enabled)
♦
MicroBlaze Processor Instruction-Side Interface (MicroBlaze system)
♦
MicroBlaze Processor Data-Side Interface (MicroBlaze system)
♦
PLB-to-OPB Bridge (PPC405 system)
OPB Slaves
♦
IIC Controller (PPC405 system)
♦
General-Purpose Input/Output (GPIO) x3
♦
16450 UART
♦
Interrupt Controller
♦
External Memory Controller x2
♦
Microprocessor Debug Module (MicroBlaze system)
♦
AC97 Sound Controller
♦
OPB-to-DCR Bridge
♦
Ethernet Controller
♦
Dual PS/2 Controller
♦
System ACE™ MPU Interface
♦
OPB-to-PLB Bridge-In (MicroBlaze system)
OPB Arbiter
for more information.
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