Online Document - Xilinx ML40 Series User Manual

Edk processor reference design
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The following conventions are used in this document:
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
Convention
Cross-reference link to a location
Blue text
in the current document
Cross-reference link to a location
Red text
in another document
Blue, underlined text
Hyperlink to a website (URL)
www.xilinx.com
Meaning or Use
Conventions
Example
See the section
"Additional
Resources"
for details.
Refer to
"Title Formats" in
Chapter 1
for details.
See
Figure 2-5
in the Virtex-II
Platform FPGA User Guide.
Go to
http://www.xilinx.com
for the latest speed files.
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