Clock/Reset Distribution - Xilinx ML40 Series User Manual

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Clock/Reset Distribution

Virtex-4 FPGAs have abundant clock management and global clock buffer resources. To
demonstrate some of these capabilities, the ML40x Embedded Processor Reference System
uses a variety of different clocks.
managers (DCMs) for generating the main clocks in the design. A 100-MHz input reference
clock is used to generate the main 100-MHz PLB, OPB, and DCR clocks. The
CLK90/180/270 output of the DCM produces a 100-MHz clock that is phase shifted by
90/180/270 degrees for use by the DDR SDRAM controller. The CLKFX output of the
DCM produces a 300-MHz processor clock for PPC405 designs. The main 100-MHz clock is
divided by four to create a 25-MHz VGA clock. A second DCM is used to recover and
deskew the external clock from the DDR SDRAM. A third DCM (not shown) is used to
deskew the externally driven SRAM clock with the internal 100-MHz clock.
Because each clock is referenced from the same 100-MHz clock, they are all phase aligned
to each other. This synchronous phase alignment is required by the CPU and many other
devices so they can pass signals from one clock domain to another.
After a system reset or at FPGA startup, a debounce circuit inside the Processor System
Reset IP Module holds the FPGA in reset until the DCM has locked onto its reference clock.
Once the DCM is locked and the clocks remain stable for several cycles, the reset condition
is released to allow the system logic to begin operating. For example, the CPU begins
fetching instructions a few cycles after reset is released. Because the reset net is a high-
fanout signal, it might not be able to reach all the logic in the design within one clock cycle.
User IP blocks should be designed to take into account the possible skew in the global reset
and still start up properly. Alternatively, the global reset can be registered locally in each IP
block to generate a synchronous reset signal.
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
Figure 2-3, page 25
Digital Clock
Manager 1
External
100 MHz
IN
Reference
Clock
Off-chip connection for board deskew
Digital Clock
Manager 2
IN
Figure 2-3: Clock Generation
www.xilinx.com
illustrates use of the digital clock
100 MHz
CLK1X
100 MHz +90°
CLK90
100 MHz +180°
CLK180
100 MHz +270°
CLK270
25 MHz
CLKDV
300 MHz
CLKFX
100 MHz +90°
CLK90
100 MHz +270°
CLK270
Hardware
PLB/OPB/OCM
DDR
Controller
VGA
PPC405
(not used in
MicroBlaze systems)
DDR
Controller
UG082_02_03_050406
25