Implementation - Xilinx ML40 Series User Manual

Chapter 6: OPB AC97 Sound Controller

Implementation

Figure 6-1, page 56
AC97 Sound Controller module manages three primary functions to control the AC97
Codec chip. It handles the playback FIFO, record FIFO, and the Codec's control/status
registers.
M
U
X
SData_In
AC97
Codec
SData_Out
AC97 Clock Domain
The playback FIFO is a 16-word deep x 16-bit wide FIFO. The playback data is stored by
alternating between left and right channel data (beginning with the left channel). This
allows the 16-entry FIFO to store a total of eight stereo data samples. Software should be
interrupt driven and programmed to refill the playback FIFO after an interrupt is received
stating that the FIFO is nearly empty. If operating in polled mode, the software should poll
the playback FIFO-full status bit and refill the FIFO when it is not full. If the playback FIFO
goes into an underrun condition (FIFO is empty and Codec requests more data), an error
flag bit is set. If the playback FIFO is underrun, the FIFO must be reset to clear the error flag
and to ensure proper operation. The FIFO threshold at which an interrupt is generated can
be set to one of four possible fullness levels. The OPB AC97 controller logic automatically
handles the process of serializing the left/right playback data and sending it out to the
Codec chip when requested.
56
shows a block diagram of the OPB AC97 Sound Controller. The OPB
OPB AC97 Sound Controller
Parallel
16
to
Serial
Serial
16
to
Parallel
7
Parallel
to
Serial
16
Parallel
to
Serial
16
Serial
to
Parallel
Figure 6-1: OPB AC97 Sound Controller Block Diagram
www.xilinx.com
16
Playback FIFO
16
Record FIFO
7
Address
Q D
16
Write Data
Q D
16
Read Data
D Q
OPB Clock Domain
ML40x EDK Processor Reference Design
R
OPB
UG082_06_01_050406
UG082 (v5.0) June 30, 2006