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Chapter 5: Using IPIF to Build IP
Basic Read Transactions
Figure 5-3
read transaction begins when the IPIF drives the address (Bus2IP_Addr) and byte enables
(Bus2IP_BE) to the IP. It qualifies the read by asserting a single clock cycle high pulse
(Bus2IP_RdReq) at the beginning of the transaction. It then waits for the IP device to
acknowledge completion of the read by sending back a single clock cycle High
acknowledge pulse on IP2Bus_RdAck. During the entire transaction from Bus2IP_RdReq
to IP2Bus_RdAck, the signal Bus2IP_SRAM_CE is held high as an enveloping signal
around the transaction. After a completed transaction, the IPIF can issue a new transaction.
Note that burst read transactions on the bus are converted into a series of single data
transfers to the IP, which all look alike.
IPIF Status and Control Signals
Extra status and control signals are also present in the SRAM protocol. If the IP2Bus_Retry
signal is asserted instead of IP2Bus_RdAck/IP2Bus_WrAck, the IPIF will assert retry on
the bus side and terminate the transaction. IP2Bus_Error asserted with
IP2Bus_RdAck/IP2Bus_WrAck will cause the IPIF to signal an error on the bus interface.
For slow IP devices, an IP2Bus_ToutSup signal can be asserted to prevent timeouts on the
bus interface. Finally the Bus2IP_Reset passes the bus-side reset to the IP.
Using IPIF to Create a GPIO Peripheral from Scratch
A General Purpose Input/Output (GPIO) peripheral can be used to show how the IPIF
simplifies new peripheral creation. The GPIO module has three 32-bit registers: one
register to control the TBUF for each I/O pin, one register to write the I/O pins, and one
register to read the I/O pins. The GPIO peripheral uses a very small amount of additional
"control logic" when used with a 32-Bit IPIF Slave SRAM module.
Figure 5-4, page 49
module using the IPIF Slave SRAM module. The IP2Bus_RdAck / IP2Bus_WrAck signals
are directly connected to the corresponding Bus2IP_RdReq / Bus2IP_WrReq signals, since
it only takes one clock cycle to read or write the GPIO registers. If more "access time" is
48
diagrams a read transaction, which looks very similar to a write transaction. A
Bus2IP_Clk
Bus2IP_Addr
Bus2IP_SRAM_CE
Bus2IP_BE
IP2Bus_Data
Bus2IP_RdReq
IP2Bus_RdAck
Figure 5-3: IPIF Simple SRAM Read Cycle
shows a conceptual view of the logic necessary to build the GPIO
www.xilinx.com
Valid
Valid
Valid
ML40x EDK Processor Reference Design
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Valid
Valid
Valid
Later Ack due
to IP response
UG082_05_03_050406
UG082 (v5.0) June 30, 2006
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