Xilinx ML40 Series User Manual page 69

R
Table 7-5: OPB PS/2 Slave Device Pin Description (Continued)
Name Field Name
Base Address + 28 INTMCLR.2
(Offset x1C) rx_full
INTMCLR.3
rx_err
INTMCLR.4
rx_ovf
INTMCLR.5
rx_ack
INTMCLR.6
rx_noack
INTMCLR.7
wdt_tout
* If software tries to read from IINTMCLR (offset x1C), the value of INTM (offset x18) is returned.
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
Bit Direction
2 R*/W Interrupt Mask Clear Register - RX data register full.
Writing a '1' to this field clears INTM.2.
Writing a '0' has no effect.
3 R*/W Interrupt Mask Clear Register - RX data error.
Writing a '1' to this field clears INTM.3.
Writing a '0' has no effect.
4 R*/W Interrupt Mask Clear Register - RX data register overflow.
Writing a '1' to this field clears INTM.4.
Writing a '0' has no effect.
5 R*/W Interrupt Mask Clear Register - TX acknowledge received.
Writing a '1' to this field clears INTM.5.
Writing a '0' has no effect
6 R*/W Interrupt Mask Clear Register - TX acknowledge not
received.
Writing a '1' to this field clears INTM.6.
Writing a '0' has no effect.
7 R*/W Interrupt Mask Clear Register - Watch dog timer timeout.
Writing a '1' to this field clears INTM.7.
Writing a '0' has no effect.
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