Basic Write Transactions - Xilinx ML40 Series User Manual

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Basic Write Transactions

Figure 5-2
when the IPIF drives the address (Bus2IP_Addr), byte enables (Bus2IP_BE), and write data
(Bus2IP_Data) to the IP. Note that the signal direction is specified in the signal name:
Bus2IP versus IP2Bus. The IPIF qualifies the write by asserting a single clock cycle High
pulse (Bus2IP_WrReq) at the beginning of the transaction. It then waits for the IP device to
acknowledge completion of the write by sending back a single clock cycle High pulse on
IP2Bus_WrAck. During the entire transaction from Bus2IP_WrReq to IP2Bus_WrAck, the
signal Bus2IP_SRAM_CE is held high as an enveloping signal around the transaction.
After a completed transaction, the IPIF can issue a new transaction. Note that burst write
transactions on the bus are converted into a series of single data transfers to the IP, which
all look alike.
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
shows the timing diagram for a write transaction. A write transaction begins
Bus2IP_Clk
Bus2IP_Addr
Bus2IP_SRAM_CE
Bus2IP_BE
Bus2IP_Data
Bus2IP_WrReq
IP2Bus_WrAck
Figure 5-2: IPIF Simple SRAM Write Cycle
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Valid
Valid
Valid
SRAM Protocol Overview of IPIF
Valid
Valid
Valid
Later Ack due
to IP response
UG082_05_02_050406
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