Chapter 4: Introduction To Hardware Reference Ip; Introduction - Xilinx ML40 Series User Manual

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Introduction to Hardware Reference IP

Introduction

The Embedded Processor Reference System contains additional hardware IP beyond what
is be shipped with the EDK tool suite. This hardware IP supports some of the features on
the ML40x board. The IP and its source code is provided as a reference example to
illustrate how hardware can be designed to interface with the Processor Local Bus (PLB),
On-chip Peripheral Bus (OPB), and Device Control Register (DCR) bus. Generally, the
interface and function of the IP is described, along with sufficient register information for
customers to use the devices. The reference IP source code is located within the pcores
directory of the ML40x Reference System's EDK project directory.
In addition to describing the individual hardware IPs, this document also introduces the
concept of the IP InterFace (IPIF) modules. These modules are designed to greatly
accelerate the process of connecting to pre-existent IP or creating new IP in a system. The
specification defines a CoreConnect compliant interface on one side and a simple interface
for connecting to existent IP on the other side.
The hardware IP uses the IBM CoreConnect bus standards as its means of communication
between the embedded processor and other devices. These standards are documented in
the IBM CoreConnect release. Please see the
information on where to find the relevant documents.
For further information on the IPIF and each IP, see:
•
•
•
•
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
Chapter 5, "Using IPIF to Build IP"
Chapter 6, "OPB AC97 Sound Controller"
Chapter 7, "OPB PS/2 Controller (Dual)"
Chapter 8, "PLB TFT LCD Controller"
www.xilinx.com
Chapter 4
"Further Reading," page 17 section for more
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