Xilinx ML40 Series User Manual page 58

Chapter 6: OPB AC97 Sound Controller
Table 6-5: Memory Map (Continued)
58
Register Address Bits
Base Address + 8 [24]
[25]
[26]
[27]
[28]
[29]
[30]
[31]
(LSB)
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Read/
Write
R Record FIFO Overrun:
0 = FIFO has not overrun
1 = FIFO has overrun
Note: Record FIFO must be reset to clear this
bit. After an overrun has occurred, the Record
FIFO will not operate properly until it is reset.
R Play FIFO Underrun:
0 = FIFO has not underrun
1 = FIFO has underrun
Note: Play FIFO must be reset to clear this bit.
After an underrun has occurred, the Play FIFO
will not operate properly until it is reset.
R Codec Ready:
0 = Codec is not ready to receive commands or
data. (This can occur during initial power-on or
immediately after reset.)
1 = Codec ready to run
R Register Access Finish:
0 = AC97 Controller waiting for access to
control/status register in Codec to complete.
1 = AC97 Controller is finished accessing the
control/status register in Codec.
Note: This bit is cleared when there is a write
to the "AC97 Control Address Register"
(described below).
R Record FIFO Empty:
0 = Record FIFO not Empty
1 = Record FIFO Empty
R Record FIFO Full:
0 = Record FIFO not Full
1 = Record FIFO Full
R Playback FIFO Half Full:
0 = Playback FIFO not Half Full
1 = Playback FIFO Half Full
R Playback FIFO Full:
0 = Playback FIFO not Full
1 = Playback FIFO Full
ML40x EDK Processor Reference Design
Description
UG082 (v5.0) June 30, 2006
R