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Chapter 7: OPB PS/2 Controller (Dual)
Module Port Interface
Information about the signals, pins, and parameters for the module is listed in tables
Table
Table 7-1: OPB Slave Signals
Table 7-2: External I/O Pins
62
7-1,
Table
7-2, and
Table 7-3, page
Name
IPIF_Rst
OPB_BE[0:3]
OPB_Select
OPB_Dbus[0:31]
OPB_Clk
OPB_Abus[0:31]
OPB_RNW
OPB_seqAddr
Sln_XferAck
Sln_Dbus[0:31]
Sln_DBusEn
Sln_errAck
Sln_retry
Sln_toutSup
Name
Sys_Intr1
Clkin1
Clkpd1
Rx1
Txpd1
Sys_Intr2
Clkin2
Clkpd2
Rx2
Txpd2
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63.
Direction
Input
OPB system reset
Input
OPB byte enables
Input
OPB select
Input
OPB data bus
Input
OPB system clock
Input
OPB address bus
Input
OPB read not write
Input
OPB sequential address
Output
Slave transfer acknowledge
Output
Slave data bus
Output
Slave data bus enable
Output
Slave error acknowledge
Output
Slave bus cycle retry
Output
Slave timeout suppress
Direction
Output
Interrupt, Port #1
Input
PS/2 Clock In, Port #1
Output
PS/2 Clock Pulldown, Port #1
Input
PS/2 Serial Data In, Port #1
Output
PS/2 Serial Data Out Pulldown, Port #1
Output
Interrupt, Port #2
Input
PS/2 Clock In, Port #2
Output
PS/2 Clock Pulldown, Port #2
Input
PS/2 Serial Data In, Port #2
Output
PS/2 Serial Data Out Pulldown, Port #2
ML40x EDK Processor Reference Design
Description
Description
UG082 (v5.0) June 30, 2006
R
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