Chapter 5: Using Ipif To Build Ip; Introduction - Xilinx ML40 Series User Manual

Edk processor reference design

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Using IPIF to Build IP

Virtex-4 devices combine embedded processors and FPGA fabric into one integrated

circuit. In the past, system development efforts relied on engineers building each

component from scratch. Today, engineers have a wide variety of microprocessor

peripherals in their IP libraries. The Intellectual Property InterFace (IPIF) is designed to

ease the creation of new IP, as well as the integration of existent IP, within a Virtex-4 device.

This chapter illustrates the utility of the IPIF to integrate IP into a system.

The IPIF modules simplify the development of CoreConnect devices. The IPIF converts

complex system buses, such as the PLB or OPB, into common interfaces, such as an SRAM

protocol or a control register interface. This makes IPIF modules ideal for quickly

developing new bus peripherals, or converting existing IP to work in a CoreConnect bus-

based system. The IPIF modules provide point-to-point interfaces using simple timing

relationships and very light protocols.

The IPIF is designed to be bus-agnostic. This allows the backend interface for the IP to

remain the same while only the bus interface logic in the IPIF is changed. It, therefore,

provides an efficient means for supporting different bus standards without change to the

IP device.

IPIF modules also provide support for DMA and interrupt functionality. The IPIF is

designed to support a wide variety of common interfaces (like SRAM, FIFO, and control

develop a custom OPB or PLB bus interface.

IPIF modules simplify driver software development because the IPIF framework contains

many common features. These include a consistent means of interrupt handling, DMA,

and organizing control/status registers.

This document demonstrates how quickly and easily a new piece of IP can be developed

using the IPIF. The process and steps for building a new CoreConnect device based on the

SRAM protocol IPIF is described below. For this sample design, a 32-bit General Purpose

I/O (GPIO) device is created. The GPIO allows a CoreConnect master such as the CPU to

control a set of external pins using a simple memory-mapped interface.

ML40x EDK Processor Reference Design

UG082 (v5.0) June 30, 2006

www.xilinx.com

Chapter 5

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