Processor Local Bus (Plb) - Xilinx ML40 Series User Manual

Edk processor reference design

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Chapter 2: ML40x Embedded Processor Reference System

Processor Local Bus (PLB)

The PLB connects the CPU to high-performance devices, such as memory controllers. The

PLB protocol supports higher bandwidth transactions and has a feature set better than

OPB/DCR. PLB supports memory operations OPB/DCR. Highlights of the PLB protocol

include synchronous architecture, independent read/write data paths, and split

transaction address/data buses. The reference design includes a 64-bit PLB infrastructure

with 64-bit master and slave devices attached.

The PLB devices in the reference system include:

•

In general, all PLB devices are optimized around the FPGA architecture and use pipelining

to improve maximum clock frequencies and reduce logic utilization. Refer to the

documentation accompanying each device for more information about its design.

PLB Masters

♦

640x480 VGA Controller

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OPB-to-PLB Bridge (MicroBlaze system)

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PPC405 Instruction-Side PLB Interface (PPC405 system)

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PPC405 Data-Side PLB Interface (PPC405 system)

PLB Slaves

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Double Data Rate (DDR) SDRAM Controller

♦

BRAM Controller (PPC405 systems)

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PLB-to-OPB Bridge (PPC405 system)

PLB Arbiter

♦

64-bit Xilinx PLB Arbiter

www.xilinx.com

ML40x EDK Processor Reference Design

UG082 (v5.0) June 30, 2006

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