Xilinx ML40 Series User Manual page 77

R
Vsync
tvp
Hsync
1 2 3
DE
R0 to R5
G0 to G5
B0 to B5
Invalid D(X,0)
DE
R0 to R5
G0 to G5
B0 to B5
Invalid
tvp = 2 h_syncs
tvb = 31 h_syncs
DE = 640 TFT Clocks
tvf = 12 h_syncs
Display period is 480 h_syncs
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
tvp
Vsync
tv = 525 h_syncs (Vertical)
tvp = 2 h_syncs
Display period is 480 h_syncs
Figure 8-4: Vsync and h_syncs
1H
tvb 480H (Fixed)
D(X,Y)
D(0,Y) D(1,Y)
Figure 8-5: Vertical Data
www.xilinx.com
tv
tvf
D(X,479)
D(X,Y) D(638,Y) D(639,Y)
Hardware
UG082_08_04_050406
1
Invalid
Note: X = 0 to 639
Invalid
UG082_08_05_050406
77