Hardware; Implementation - Xilinx ML40 Series User Manual

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Hardware

Implementation

Figure 8-1
has a PLB master interface that reads pixel data from an external PLB memory device. It
reads the pixel data for each display line using a series of 16-doubleword burst
transactions. The pixel data is stored in an internal line buffer and then sent out to the TFT
display with the necessary timing to correctly display the image. The video memory is
arranged so that each RGB pixel is represented by a 32-bit word in memory (see
Map," page
then displayed. This process repeats continuously over every line and frame to be
displayed on the 640x480 VGA TFT screen.
The backend logic driving the TFT display operates in the same clock domain as the video
clock. It reads out data from the dual port line buffer and transmits the pixel data to the
TFT. The backend logic automatically handles the timing of all the video synchronization
signals, including back porch and front porch blanking. See
more information.
The PLB TFT LCD Controller allows for the PLB clock and TFT video clocks to be
asynchronous to each other. Special logic allows control signals to be passed between
asynchronous PLB and TFT clock domains. A dual port BRAM is used as the line buffer to
pass video data between the two clock domains.
It is important to design the system so that there is sufficient bandwidth between the PLB
TFT LCD Controller and the PLB memory device to meet the video bandwidth
requirements of the TFT. Furthermore, there must be enough available bandwidth
remaining for the rest of the system. If more bandwidth is needed for the rest of the system,
the TFT clock frequency can be reduced. However, reducing the TFT clock frequency also
lowers the refresh rate of the screen. This leads to a noticeable flicker on the screen if the
TFT clock is too slow.
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
shows a high-level block diagram of the design. The PLB TFT LCD Controller
78). As each line interval begins, data is fetched from memory, buffered, and
TFT
Interface
Video Signals
Logic
to TFT Display
TFT Clock Domain
Figure 8-1: High-Level Block Diagram
www.xilinx.com
Get Line
Synchronizer
10
Column Addr
6
Red Data
1 kB x 18 bit
Dual Port
BRAM
6
Green Data
6
Blue Data
Hardware
"Memory
10
Column Addr
PLB
Interface
6
Red Data
Logic
(Master)
6
Green Data
6
Blue Data
PLB Clock Domain
UG082_08_01_050406
"Video Timing," page 76
PLB
for
75