Ml40X Single-Ended Expansion Header General Purpose I/O Registers - Xilinx ML40 Series User Manual

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ML40x Single-Ended Expansion Header General Purpose I/O Registers

Table 2-8
GPIO data/direction registers at address 0x90001008-0x9000100C.
Table 2-8: Single-Ended Expansion Header GPIO Regs (Addr 0x90001008-0x9000100C)
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
shows the single-ended expansion header registers, which are a standard set of
Bit Description
0 J6, Pin 2
1 J6, Pin 4
2 J6, Pin 6
3 J6, Pin 8
4 J6, Pin 10
5 J6, Pin 12
6 J6, Pin 14
7 J6, Pin 16
8 J6, Pin 18
9 J6, Pin 20
10 J6, Pin 22
11 J6, Pin 24
12 J6, Pin 26
13 J6, Pin 28
14 J6, Pin 30
15 J6, Pin 32
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ML40x Specific Registers
Bit Description
16 J6, Pin 34
17 J6, Pin 36
18 J6, Pin 38
19 J6, Pin 40
20 J6, Pin 42
21 J6, Pin 44
22 J6, Pin 46
23 J6, Pin 48
24 J6, Pin 50
25 J6, Pin 52
26 J6, Pin 54
27 J6, Pin 56
28 J6, Pin 58
29 J6, Pin 60
30 J6, Pin 62
31 J6, Pin 64
33