Ml40X Control Register 1 - Xilinx ML40 Series User Manual

Chapter 2: ML40x Embedded Processor Reference System
Table 2-3: GPIO Registers (Address 0x90000000-0x90000004) (Continued)

ML40x Control Register 1

Table 2-4
Table 2-4: Control Register 1 (Address 0x90000008)
30
Bit(s)
25 SMA "Output P"(ML401/ML403/ML405 only)
26 User Clock (ML401/ML403/ML405 only)
27 IIC Bus Select 0 (ML405 only)
28 IIC Bus Select 1 (ML405 only)
31-29 (MSB) Reserved
Note: A 1 value indicates a button was pushed or turns ON an LED.
shows Control Register 1 located at address 0x90000008.
Bit(s)
0 (LSB) IIC SCL. Valid only when IIC GPIO is enabled (see
2," Bit 6). Reading this bit reads the value from the external pin. Writing this bit
sets the value of the external pin if the corresponding direction bit is set to a
"write" (see
1 IIC SDA. Valid only when IIC GPIO is enabled (see
Bit 6). Reading this bit reads the value from the external pin. Writing this bit sets the
value of the external pin if the corresponding direction bit is set to a "write" (see
"ML40x Control Register 2,"
7-2 Reserved.
8 PS/2 Mouse Clock. Valid only when PS/2 GPIO is enabled (see
Register 2," Bit 7). Reading this bit reads the value from the external pin. Writing
this bit sets the value of the external pin if the corresponding direction bit is set to a
"write" (see "ML40x Control Register 2,"
9 PS/2 Mouse Data. Valid only when PS/2 GPIO is enabled (see
Register 2," Bit 7). Reading this bit reads the value from the external pin. Writing
this bit sets the value of the external pin if the corresponding direction bit is set to a
"write" (see "ML40x Control Register 2,"
10 PS/2 Keyboard Clock. Valid only when PS/2 GPIO is enabled (see
Register 2," Bit 7). Reading this bit reads the value from the external pin. Writing
this bit sets the value of the external pin if the corresponding direction bit is set to a
"write" (see "ML40x Control Register 2,"
11 PS/2 Keyboard Data. Valid only when PS/2 GPIO is enabled (see
Register 2," Bit 7). Reading this bit reads the value from the external pin. Writing
this bit sets the value of the external pin if the corresponding direction bit is set to a
"write" (see "ML40x Control Register 2,"
12 CPU Reset Button. Valid only when CPU Reset GPIO is enabled (see
Control Register 2,"
A "1" value indicates the CPU reset button was pushed.
31-13 (MSB) Reserved.
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Description
Description
"ML40x Control Register 2,"
Bit 1).
Bit 12). Reading this bit reads the value from the external pin.
"ML40x Control Register
Bit 0).
"ML40x Control Register 2,"
"ML40x Control
Bit 8).
"ML40x Control
Bit 9).
"ML40x Control
Bit 10).
"ML40x Control
Bit 11).
"ML40x
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
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