Implementation - Xilinx ML40 Series User Manual

Chapter 7: OPB PS/2 Controller (Dual)

Implementation

Figure 7-1
with an SRAM interface in addition to simple state machines and shift registers to
implement its functionality. Each PS/2 port is controlled by a separate set of eight byte-
wide registers.
For transmitting data, a byte write to the transmit register causes that data to be serialized
and sent to the PS/2 device. Status registers and interrupts then signal when the
transmission is complete and if there are any errors reported. Similarly, receiver status
registers and interrupts signal when data has been received from the PS/2 device. Any
errors with received data are also reported.
The PS/2 controller can be operated in a polled mode or an interrupt driven mode. In the
interrupt driven mode, separate register bits for setting, clearing, and masking of
individual interrupts are provided.
Because the PS/2 interface uses an open collector circuit for transmitting data, the output
signals Clkpd and Txpd should be tied to a transistor or logic gate capable of pulling the
5V PS/2 clock and data signals low. Note that the PS/2 protocol specifies 5V signalling.
Therefore, it is necessary to have the proper interface circuitry to prevent over-voltage
conditions on the FPGA I/O. Consult the schematics and documentation for the Xilinx
ML40x board for an example implementation of a PS/2 port interface circuit.
64
shows a block diagram of the OPB PS/2 Controller module. It uses an IPIF slave
OPB
Registers
ps2_reg.v
OPB
Slave
IPIF
Registers
ps2_reg.v
Figure 7-1: OPB PS/2 Controller Block Diagram
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Misc control logic
Memory
Mapped
TX State Machine
RX State Machine
ps2_sie.v
Misc control logic
Memory
Mapped
TX State Machine
RX State Machine
ps2_sie.v
ML40x EDK Processor Reference Design
PS2_1_DATA_OUT
Shift PS2_1_DATA_IN
Registers
and
PS2_1_CLK_OUT
Clock
Controls
PS2_1_CLK_IN
PS2_2_DATA_OUT
Shift
PS2_2_DATA_IN
Registers
and
Clock PS2_2_CLK_OUT
Controls
PS2_2_CLK_IN
UG082_07_01_050406
UG082 (v5.0) June 30, 2006
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