Xilinx ML40 Series User Manual page 67

R
Table 7-5: OPB PS/2 Slave Device Pin Description (Continued)
Name Field Name
Base Address + 16 INSTA.2
(Offset x10) rx_full
INSTA.3
rx_err
INSTA.4
rx_ovf
INSTA.5
tx_ackf
INSTA.6
tx_noack
INSTA.7
wdt_tout
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
Bit Direction
2 R Interrupt Status Register - RX data register full.
This field is updated by the PS/2 Serial Interface when the
SIE has received a data packet. Software clears this field by
writing a '1' into the corresponding interrupt clear register
INTCLR.2 (offset x14.2)
3 R Interrupt Status Register - RX data error.
This field is updated by the PS/2 Serial Interface when the
SIE has found that RX data is a bad packet. Software clears
this field by writing a '1' into the corresponding interrupt
clear register INTCLR.3 (offset x14.3)
4 R Interrupt Status Register - RX data register overflow.
This field is updated by the PS/2 Serial Interface when the
SIE overwrites a data packet before the previous data was
read. Software clears this field by writing a '1' into the
corresponding interrupt clear register INTCLR.4 (offset
x14.4)
5 R Interrupt Status Register - TX acknowledge received.
This field is updated by the PS/2 Serial Interface when the
SIE completes transmission of a data byte and has received
acknowledgement from the PS/2 device.Software clears this
field by writing an '1' into the corresponding interrupt clear
register INTCLR.5 (offset x14.5)
6 R Interrupt Status Register - TX acknowledge not received.
This field is updated by the PS/2 Serial Interface when the
SIE completes transmission of a data byte but has not yet
received acknowledgement from the PS/2 device.Software
clears this field by writing an '1' into the corresponding
interrupt clear register INTCLR.6 (offset x14.6)
7 R Interrupt Status Register - Watch dog timer timeout.
This field is updated by the PS/2 Serial Interface when the
SIE does not receive a PS/2 Clock while a packet is still being
transmitted. Software clears this field by writing an '1' into
the corresponding interrupt clear register INTCLR.7 (offset
x14.7)
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