Xilinx ML40 Series User Manual page 49

R
required by the registers, a simple SRL16-based shift register between the Req/Ack signals
could be used to set the number of cycles the register will respond in. An example use of
this function is to gain timing margin by treating the register access as a multicycle path.
This simple enhancement to the IPIF can have very positive effects in meeting the timing
requirements typical of complex microprocessor-based systems. Note that register
response time can be tuned differently between the read and the write.
T
O
I
To drive an external I/O pin, the output enable for that pin must be asserted, allowing the
pin to be driven High or Low based upon the contents of the write register. If the output
enable for a given pin is deasserted, the pin's driver is put in a high impedance state,
allowing an external device to drive the pin. The CPU can sense the current value of any
pin (regardless of its direction) by reading the read register. Driving the direction of the
I/O pin is controlled by the contents of the three-state register.
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
S
[0 :7 ]
Q D
C E
C
S
[8 :1 5]
Q D
C E
C
S
[1 6: 2 3]
Q D
C E
C
S
[2 4: 3 1]
Q D
C E
C
[0 :7 ]
Q D
C E
C
[ 8 :1 5]
Q D
C E
C
[1 6: 2 3]
Q D
C E
C
[2 4: 3 1]
Q D
C E
C
[0 :3 1 ]
[0: 31 ]
D Q
C
Figure 5-4: IPIF SRAM Module to GPIO Logic Interface
www.xilinx.com
Using IPIF to Create a GPIO Peripheral from Scratch
B us 2I P _Re set
[0 :7 ]
W r Re q
B E[ 0]
A ddr [ 29 ]
[8 :1 5]
W r Re q
B E[ 1]
A ddr [ 29 ]
[ 16 :2 3]
W r Re q
B E[ 2]
A ddr [ 29 ]
[2 4: 31]
W r Re q
B E[ 3]
A ddr [ 29 ]
[ 0: 7]
W r Re q
B E[ 0]
A ddr [ 29 ]
[8 :1 5]
W r Re q
B E[ 1]
A ddr [ 29 ]
[1 6: 2 3 ]
W r Re q
B E[ 2]
A ddr [ 29 ]
[2 4: 31]
W r Re q
B E[ 3]
A ddr [ 29 ]
A ddr [ 29 ]
1
0
Bu s 2 IP _Cl k
Bu s 2 IP _A dd r [0 :3 1]
B us 2I P_ D at a[0 :3 1]
OP B
IP 2B u s _D a ta[ 0:3 1]
B us 2I P_ BE [ 0: 3]
IP I F
S l ave
Bu s 2 IP _ S RAM_CE
M od ul e
B us 2I P_ Wr Re q
IP 2B u s _W r A ck
B us 2I P_ RdRe q
IP 2B u s _Rd Ack
IP 2B u s _Re tr y
IP 2B u s _E r r or
IP 2B u s_Tout S u p
B us 2I P_ Re s et
U G 08 2_ 05_04 _0 504 06
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