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Chapter 4: Introduction to Hardware Reference IP
Hardware Reference IP Source Format and Size
The hardware reference IP available with the ML40x Embedded Processor Reference
System originates in one language as either Verilog or VHDL source code. IP delivered in
Verilog or VHDL source format is directly viewable and editable by the user as a text file.
The EDK tools handle the process of building systems consisting of a mixture of IP written
in different languages. For example, the PLB TFT LCD Controller is available only in
Verilog source code, so the EDK tools need to convert the design into a blackbox netlist for
use in a top-level VHDL-based design.
Table 4-1
these cores. Many of the IP blocks are parameterizeable so their size might increase or
decrease depending on how they are configured. These area numbers represent a full
implementation of each IP synthesized with the Xilinx tool XST. It is important to note that
when IP is connected together in a system, logic optimizations and resource sharing can
further reduce the overall logic count. Slice utilization is only an estimate because the
packing of lookup tables (LUTs) and flip-flops (FFs) into slices depends on the overall
system implementation.
Table 4-1: Hardware Reference IP and Logic Utilization
These are all titles of individual document types in a book. Some are autonumbered, some
are not.
44
provides information about the source code format and resource utilization for
Name
OPB AC97 Sound Controller
OPB PS/2 Controller
PLB TFT LCD Controller
www.xilinx.com
Source Code
Format
Slice
Verilog VHDL
FFs
X
183
X
265
X
276
ML40x EDK Processor Reference Design
Logic Utilization
Slices
Block
LUTs
(Est)
RAMs
204
151
0
430
236
0
289
193
1
UG082 (v5.0) June 30, 2006
R
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