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Chapter 6: OPB AC97 Sound Controller
Module Port Interface
Information about the signals, pins, and parameters for the module is listed in tables
Table
Table 6-1: Global Signals
Table 6-2: OPB Slave Signals
Table 6-3: External I/O Pins
54
6-1,
Table
6-2,
Table
6-3,
Name
OPB_Clk
OPB_Rst
Name
OPB_ABus[0:31]
OPB_BE[0:3]
OPB_DBus[0:31]
OPB_RNW
OPB_select
OPB_seqAddr
OPB_AC97_CONTROLLER_DBus[0:31]
OPB_AC97_CONTROLLER_errAck
OPB_AC97_CONTROLLER_retry
OPB_AC97_CONTROLLER_toutSup
OPB_AC97_CONTROLLER_xferAck
Name
Playback_Interrupt
Record_Interrupt
Bit_Clk
Sync
SData_Out
SData_In
www.xilinx.com
Table 6-4, page
55.
Direction
Input
OPB system clock
Input
OPB system reset
Direction
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Direction
Output
Interrupt generated when play buffer fullness is
at or below programmed threshold.
Output
Interrupt generated when record buffer fullness
is at or above programmed threshold.
Input
Serial Bit Clock from AC97 Codec.
Output
Frame synchronization signal to AC97 Codec.
Output
Serial Data output to AC97 Codec.
Input
Serial Data input from AC97 Codec.
ML40x EDK Processor Reference Design
Description
Description
OPB address bus
OPB byte enables
OPB data bus
OPB read-not-write
OPB select
OPB sequential address
Slave data bus
Slave error acknowledge
Slave bus cycle retry
Slave time-out suppress
Slave transfer acknowledge
Description
UG082 (v5.0) June 30, 2006
R
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