Xilinx ML40 Series User Manual page 74

Chapter 8: PLB TFT LCD Controller
Table 8-5: Parameters
74
Name
C_DCR_BASEADDR
C_DCR_HIGHADDR
C_DEAFULT_TFT_BASE_ADDR[0:10]
C_DPS_INIT
C_ON_INIT
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Default Description
N/A Base address of DCR control registers.
Must be aligned on an even DCR
address boundary (least significant bit
= 0).
N/A Upper address boundary, must be set to
value of C_DCR_BASEADDR + 1.
N/A Most significant bits of base address for
video memory. The 11 most significant
bits of this address define the 2 MB
region of memory used for the video
frame storage.
1 Initial reset state of DPS control bit:
0 = DPS output bit resets to 0.
This initializes the display to use a
normal scan direction.
1 = DPS output bit resets to 1.
This initializes the display to use a
reverse scan direction (rotates screen
180 degrees).
1 Initial reset state of TFT enable/disable
bit:
0 = Disable TFT display on reset.
This causes a black screen to be
displayed on reset.
1 = Enable TFT display on reset.
This causes the PLB TFT LCD
controller to operate normally on
reset.
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
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