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ML40x Embedded Processor Reference
System
Introduction
The ML40x Embedded Processor Reference System is an example of a large Virtex-4 based
system. An IBM Core Connect infrastructure connects the CPU to numerous peripherals
using Processor Local Bus (PLB), On-Chip Peripheral Bus (OPB), and Device Control
Register (DCR) buses to build a complete system. This document describes the contents of
the reference system and provides information about how the system is organized and
implemented. A complete design cycle incorporating synthesis, FPGA implementation,
and download is described. The information introduces many aspects of the ML40x
Embedded Processor Reference System, but the user should refer to additional specific
documentation for more detailed information about the software, tools, peripherals,
interface protocols, and capabilities of the FPGA.
Hardware
Overview
Figure 2-1, page 20
MicroBlaze Processor System.
PPC405-based system for ML403. These designs demonstrate a system that uses PLB, OPB,
and DCR devices. The PLB protocol generally supports higher bandwidths, so the high-
bandwidth devices are placed there. The OPB connects the lower-performance peripheral
devices to the CPU. The OPB offers a less complex protocol relative to the PLB, making it
easier to design peripherals that do not require the highest performance. The OPB also has
the advantage that it can support a greater number of devices. DCR is used with control
and status registers for simplicity when performance is not important. Refer to the PLB,
OPB, and DCR CoreConnect Architecture Specifications for more information. The
hardware devices used in this design are described in more detail in the Processor IP
Reference Guide (see <EDK Install Directory>/doc/proc_ip_ref_guide.pdf)
and in
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
provides a high-level view of the hardware contents of the Embedded
Figure 2-2, page 21
Chapter 4, "Introduction to Hardware Reference IP."
www.xilinx.com
Chapter 2
provides an overview of the
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