Memory Map - Xilinx ML40 Series User Manual

R
The record FIFO is a 16-word deep x 16-bit wide FIFO. The record data is stored in an
alternating fashion between left and right channel data (beginning with the left channel).
This allows the 16-entry FIFO to store a total of eight stereo data samples. Software should
be interrupt driven and programmed to empty the record FIFO after an interrupt is
received stating that the FIFO is nearly full. If operating in polled mode, the software
should poll the playback FIFO-empty status bit and get data from the FIFO when it is not
empty. If the record FIFO goes into an overrun condition (FIFO is full and Codec sends
more data), an error flag bit is set. If the record FIFO is overrun, the FIFO must be reset to
clear the error flag and to ensure proper operation. The FIFO threshold at which an
interrupt is generated can be set to one of four possible emptiness levels. The OPB AC97
controller logic automatically handles the process of parallelizing the left/right serial
record data that is received from the Codec chip.
The playback and record FIFOs must be operated with the same sampling frequency
between the left and right channels. The FIFO logic does not support the left and right
channels operating at different frequencies.
Access to the control/status registers in the Codec chip is performed through a set of
keyhole registers. To write to the control registers in the Codec chip, the write data and
then the address to be accessed are written to two registers in the OPB AC97 controller.
This causes the write data to be serialized and sent to the Codec chip. A status bit signals
when the write is complete. Reading a status register in the Codec chip is performed in a
similar manner. The read address is written to the OPB AC97 controller. This causes a read
command to be serialized and sent to the Codec chip. When the Codec chip responds with
the read data, a status bit is set indicating that the return data is available. See the
Map"
The Bit_Clk from the AC97 Codec chip typically runs at a frequency of 12.288 MHz while
the OPB clock runs with a typical frequency of 50-100 MHz. Because of the asynchronous
relationship between these two clock domains, the OPB AC97 controller contains special
logic to pass data between these two clock domains. In order for this synchronizing logic to
function properly, it is important that the OPB clock frequency is at least two times higher
than the AC97 Bit_Clk frequency.

Memory Map

Information about the memory mapped registers is shown in
multiple pages).
Table 6-5: Memory Map
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
section for more information about using these registers.
Register Address Bits
Base Address + 0 [16:31]
Base Address + 4 [16:31]
www.xilinx.com
Read/
Write
W Write 16-bit data sample to playback FIFO. Data
should be written two at a time to write data to the
left channel followed by the right channel.
R Read 16-bit data sample from record FIFO. Data
should be read two at a time to get data from the left
channel followed by the right channel.
Memory Map
"Memory
Table 6-5 (which spans
Description
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