Xilinx ML40 Series User Manual page 63

Edk processor reference design
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Table 7-3: Parameters
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
Name
C_BASEADDR
32-bit base address of PS/2 controller (must be aligned to 8-KB
boundary)
C_HIGHADDR
Upper address boundary, must be set to value of
C_BASEADDR + 0x1FFF (8-KB boundary)
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Module Port Interface
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