Ml40X Character Lcd General Purpose I/O Registers; Ml40X Differential Expansion Header General Purpose I/O Registers - Xilinx ML40 Series User Manual

Chapter 2: ML40x Embedded Processor Reference System

ML40x Character LCD General Purpose I/O Registers

Table 2-6
data/direction registers at address 0x90002000-0x90002004.
Table 2-6: Character LCD GPIO Registers (Address 0x90002000-0x90002004)

ML40x Differential Expansion Header General Purpose I/O Registers

Table 2-7
GPIO data/direction registers at address 0x90001000-0x90001004.
Table 2-7:
32
shows the character LCD registers, which are a standard set of GPIO
Bit(s)
0 (LSB) Character LCD Pin "DB4"
1 Character LCD Pin "DB5"
2 Character LCD Pin "DB6"
3 Character LCD Pin "DB7"
4 Character LCD Pin "RW"
5 Character LCD Pin "RS"
6 Character LCD Pin "E"
31-7 (MSB) Reserved
shows the differential expansion header registers, which are a standard set of
Differential Expansion Header GPIO Regs (Addr 0x90001000-0x90001004)
Bit Description
1-0 J5, Pin 4; J5, Pin 2
3-2 J5, Pin 8; J5, Pin 6
5-4 J5, Pin 12; J5, Pin 10
7-6 J5, Pin 16; J5, Pin 14
9-8 J5, Pin 20; J5, Pin 18
11-10 J5, Pin 24; J5, Pin 22
13-12 J5, Pin 28; J5, Pin 26
15-14 J5, Pin 32; J5, Pin 30
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Description
Bit Description
17-16 J5, Pin 36; J5, Pin 34
19-18 J5, Pin 40; J5, Pin 38
21-20 J5, Pin 44; J5, Pin 42
23-22 J5, Pin 48; J5, Pin 46
25-24 J5, Pin 52; J5, Pin 50
27-26 J5, Pin 56; J5, Pin 54
29-28 J5, Pin 60; J5, Pin 58
31-30 J5, Pin 64; J5, Pin 62
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
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