Memory Map - Xilinx ML40 Series User Manual

R

Memory Map

Information about the memory mapped registers is shown in
Note:
1.
2.
Table 7-4: Memory Map Table
Offset Bit Bit Bit
0 1
x00 Reserved
x04 Reserved
x08 RXR
x0c TXR
x10 Reserved INSTA.2
rx_full
x14 Reserved INTCLR.2
rx_full
x18 Reserved INTMSET.2
rx_full
x1c Reserved INTMCLR.2
rx_full
*
R = Reserved
All fields marked Reserved return zero. The field in INTSTA(x10) is AND'ed with the fields
in INTM(x18), then the bits get OR'ed to form a single Interrupt signal.
The register pairs INTSTA/INTCLR and INTMSET/INTMCLR are implemented to allow
single bit register updates which reduce the latency of interrupt handling. INTCLR and
INTMCLR are helper functions that make setting and clearing the Interrupt Status Register
and Interrupt Mask Register faster.
The register definitions are shown in
Note:
0x1000.
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
Control/status registers for PS/2 Port #1 start at the base address
(value of parameter C_BASEADDR).
Control/status registers for PS/2 Port #2 start at the base address + 0x1000
(value of parameter C_BASEADDR + 0x1000).
Bit
2 3
INSTA.3 INSTA.4
rx_err rx_ovf
INTCLR.3 INTCLR.4
rx_err rx_ovf
INTMSET.3 INTMSET.4
rx_err rx_ovf
INTMCLR.3 INTMCLR.4
rx_err rx_ovf
The second PS/2 Port has an identical set of control/status registers at an additional offset of
www.xilinx.com
Bit Bit
4 5
STR.6
tx_full_sta
INSTA.5 INSTA.6
tx_ackf tx_noack
INTCLR.5 INTCLR.6
tx_ackf tx_noack
INTMSET.5 INTMSET.6
tx_ackf tx_noack
INTMCLR.5 INTMCLR.6
tx_ackf tx_noack
Table 7-5, page 66
Memory Map
Table 7-4.
Bit Bit
6 7
SRST
STR.7
rx_full_sta
INSTA.7
wdt_tout
INTCLR.7
wdt_tout
INTMSET.7
wdt_tout
INTMCLR.7
wdt_tout
(this table spans several pages).
Bit
8-31
R*
R*
R*
R*
R*
R*
R*
R*
65