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Chapter 2: ML40x Embedded Processor Reference System
CPU Debug via JTAG
The CPU in the ML40x Embedded Processor Reference System can be debugged via JTAG
using the EDK tools.
The preferred method of communicating with the CPU via JTAG is to combine the CPU
JTAG chain with the FPGA's main JTAG chain, which is also used to download bitstreams.
For MicroBlaze designs, this method requires the user to instantiate an OPB MDM
component and directly connect it to the CPU in the user's design. For PPC405 designs, a
JTAGPPC component must be instantiated and connected to the PPC405 processor. The
primary advantage of sharing the same JTAG chain for CPU debug and FPGA
programming is that this simplifies the number of cables needed; a single JTAG cable (like
the Xilinx Parallel Cable IV cable) can be used for bitstream download as well as CPU
software debugging.
Error LEDs
The design contains two* error LED outputs to signal OPB (Error 1) and PLB (Error 2)
errors. OPB errors (Error 1 LED on the ML40x board) signal an OPB timeout or OPB error
acknowledge condition. PLB errors (Error 2 LED on the ML40x board) signal a PLB
timeout or data error acknowledge condition as reported by the PLB arbiter. Control
registers in the design allow the error conditions to be cleared. See
Register 2," page 31
Note:
OPB error conditions.
IP Version and Source
Table 2-1
ML40x Embedded Processor Reference System. The table shows the hardware version
number of each IP core used in the design. The table also lists whether the source of the IP
is from the EDK installation or whether it is reference IP in the local pcores directory.
Table 2-1: IP Cores in the ML40x Embedded Processor Reference System
26
for more information.
*On the ML403 and ML405 boards, only the Error 1 LED is present. It signals both PLB and
(which spans multiple pages) summarizes the list of IP cores making up the
Hardware IP
bram_block
dcm_module
dcr_v29
jtagppc_cntlr
(PPC405 systems)
lmb_bram_if_cntlr
(MicroBlaze systems)
lmb_v10
(MicroBlaze systems)
microblaze
misc_logic
opb_ac97_controller_ref
opb_emc
www.xilinx.com
Version
1.00.a
EDK Installation
1.00.a
EDK Installation
1.00.a
EDK Installation
2.00.a
EDK Installation
pcores Directory
1.00.b
Local
1.00.a
EDK Installation
4.00.a
EDK Installation
pcores Directory
1.00.a
Local
pcores Directory
1.00.a
Local
2.00.a
EDK Installation
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
R
"ML40x Control
Source
(1)
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