Control Registers (Dcr Interface) - Xilinx ML40 Series User Manual

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Control Registers (DCR Interface)

The register definitions are shown in
Table 8-7: Control Registers (DCR Interface)
ML40x EDK Processor Reference Design
UG082 (v5.0) June 30, 2006
Register Address
DCR Base Address + 0
DCR Base Address + 1
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Table 8-7.
Bits Read/Write
[31:0] RW Base Address of video memory. This is
the address of a PLB accessible memory
device that acts as the video memory.
This address must be aligned on a 2 MB
boundary (i.e., only the upper 11 bits are
writable and the remaining address bits
are always 0).
[31:2] - Undefined.
[1] RW DPS control bit:
0 = Set DPS output bit to 0. This sets
the display to use a normal scan
direction.
1 = Set DPS output bit to 1. This sets
the display to use a reverse scan
direction (rotates screen 180 degrees).
[0] RW TFT enable/disable bit:
0 = Disable TFT display. This causes a
black screen to be displayed and it
disables the generation of PLB read
transactions.
1 = Enable TFT display. This causes the
PLB TFT LCD controller to operate
normally.
Memory Map
Description
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