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R
DRP DCM Implementation
The DRP implementation allows dynamic adjustment of M, D, and PS values (direct mode)
in the DCM. The following ports are available in DCM_ADV primitive (see Chapter 2 of
the
Inputs:
Outputs:
DADDR[6:0] is latched at DCLK rising edge while DEN is asserted. The DO output reflects
the status of that latched address location. After reset, the internal address is reset to 0, and
the DCM DRP DO outputs are used to signal the default status Phase Shift Overflow,
CLKIN Stopped, CLKFX Stopped, and CLKFB Stopped. However, if the DRP is used to
reprogram M, D, or PS value, the DO is no longer showing default status. To access default
status, the user must perform a DRP read with DADDR[6:0] = 0.
Changing the Multiply and Divide Values
The Multiply and Divide (M/D) values can be directly programmed in the DCM through
the DRP by writing to hex addresses 50h and 52h respectively. The five least-significant
data bits represent the multiply-minus-1 and divide-minus-1 values, as shown in
and
The DCM must be held in reset by activating input RST while changing the M/D values.
At some point after RST is released, signal LOCKED goes true, indicating that the clock
outputs of the DCM are valid.
Table 6-2: Multiplier Settings
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Virtex-4 FPGA User
Guide):
DI[15:0]
DADDR[6:0]
DWE
DEN
DCLK
DO[15:0]
DRDY
Table
6-3. DRDY indicates that the new value has been written successfully.
DADDR[15:0]
DEC
50h
0000
50h
0001
50h
0002
50h
0003
50h
0004
•
•
•
•
•
•
50h
0030
50h
0031
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Dynamic Reconfiguration of Functional Blocks (DRP)
DI[15:0]
0000h (0000000000000000)
0001h (0000000000000001)
0002h (0000000000000010)
0003h (0000000000000011)
0004h (0000000000000100)
•
•
•
001Eh (0000000000011110)
001Fh (0000000000011111)
Table 6-2
Function
N/A
Multiply by 2
Multiply by 3
Multiply by 4
Multiply by 5
•
•
•
Multiply by 31
Multiply by 32
83
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