Mitsubishi Electric MELSEC Q Series User Manual page 273

(b) Precautions
Old and new data may be mixed in the data for CPU No. depending on the following timing.
• Timing when data writing to the user setting area by another module and read-out from the host module to
another module's user setting area takes place simultaneously.
• Timing when data writing to the user setting area by the host module and read-out from another module to
the host module's user setting area takes place simultaneously.
Therefore, configure an interlock program for auto refresh so that data of another CPU will not be used when
old and new data are mixed.
The following example user setting area in the multiple CPU high speed transmission area show an example
program to perform interlock in data transmission from No.1 module (C Controller module) to No.2 module (C
Controller module).
Sending side program for CPU No.1
CHAPTER 14 FUNCTIONS USED BY MULTIPLE CPU SYSTEM
Processing flow
(The numbers from 1) through 9) represent
the execution sequence.))
1) Transmitted data are written into the user setting area.
2) Data set complete bit ON is written into the user setting
area.
The multiple CPU high speed transmission area data in
the No.1 module are automatically transmitted to the No.2
module.
6) Received data processing complete bit ON is detected.
7) The data set complete bit is turned OFF.
The multiple CPU high speed transmission area data in
the No.1 module are automatically transmitted to the No.2
module.
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