Mitsubishi Electric MELSEC Q Series User Manual page 261

(4) Precautions
Depending on the timing of writing data to the host CPU's auto refresh area or reading data from another CPU,
old and new data may be mixed in the area for each CPU.
Therefore, configure an interlock program for auto refresh so that data of another CPU will not be used when old
and new data are mixed.
The following parameter settings show an example program to perform interlock in data transmission from
No.1 module (programmable controller CPU) to No.2 module (C Controller module).
Auto refresh setting for CPU No.1
CPU specific send
CPU Setting
No. No.
Points
Setting 1 2
No.1
Setting 2 10
No.2 Setting 1 2
*1 : M0 as an interlock device (Data set completion bit) of CPU No.1.
*2 : M32 as an interlock device (Data processing completion bit) of CPU No.2.
Sending side program(CPU No.1)
Write
command
M100 M0
7)
M0 M32
CPU side
range device
Start End Start End
*1
0 1
M0
2 11 D0
*2
0 1
M32
1)
M32
Set send data in
D0 to D9.
2)
SET M0
RST M0
RST M100
CHAPTER 14 FUNCTIONS USED BY MULTIPLE CPU SYSTEM
Auto refresh setting for CPU No.2
Direction
CPU Setting
No.
M31 Setting 1

No.1
D9 Setting 2

M63 No.2 Setting 1
(The numbers from 1) through 9)
represent the execution sequence.)
1) Transmission data are stored in D0-D9.
2) The data set complete bit (M0) is turned ON.
END processing by the No.1 module writes the
above data into the auto refresh area in the
No.1 transmission area of the host station.
Data in the auto refresh area in the No.1
transmission area are transmitted to the No.2
module.
7) END processing reads the data from the auto
refresh area in the No.1 module's No.2
transmission area into the specified device.
Data processing complete bit (M32) ON is
detected.
The data set complete bit (M0) is turned OFF.
CPU specific send
range
No.
Points Start End
2 0
10 2
2 0
Processing flow
259
1
11
14
1