Register Descriptions; Table 7.18 Port A Registers - Hitachi H8/3062 Hardware Manual

7.11.2

Register Descriptions

Table 7.18 summarizes the registers of port A.

Table 7.18 Port A Registers

Address *
Name
H'EE009 Port A data direction
register
H'FFFD9 Port A data register
Note: * Lower 20 bits of the address in advanced mode
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
Bit
PA DDR
Initial value
Modes
3 and 4
Read/Write
Modes
Initial value
1, 2, 5,
Read/Write
6 and 7
The pin functions that can be selected for pins PA
modes 3 to 5. For the method of selecting the pin functions, see tables 7.19 and 7.20.
The pin functions that can be selected for pins PA
method of selecting the pin functions, see table 7.21.
When port A functions as an input/output port, a pin in port A becomes an output port if the
corresponding PADDR bit is set to 1, and an input port if this bit is cleared to 0. In modes 3 and 4,
PA DDR is fixed at 1 and PA
7
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, 6, and 7.
It is initialized to H'80 by a reset and in hardware standby mode in modes 3 and 4. In software
standby mode it retains its previous setting. Therefore, if a transition is made to software standby
202
PADDR
PADR
7 6
PA DDR PA DDR
7 6 5
1 0
— W W
0 0
W W W
functions as the A
7
R/W Modes 1, 2, 5, 6 and 7
W H'00
R/W H'00
5 4 3
PA DDR PA DDR
4 3
0 0 0
W W
0 0 0
W W
Port A data direction 7 to 0
These bits select input or output for port A pins
to PA differ between modes 1, 2, 6, and 7, and
7 4
to PA are the same in modes 1 to 7. For the
3 0
address output pin.
20
Initial Value
Modes 3, 4
H'80
H'00
2 1
PA DDR PA DDR PA DDR
2 1
0 0
W W
0 0
W W
0
0
0
W
0
W