Figure 8.3 Block Diagram Of Channel 2 - Hitachi H8/3062 Hardware Manual

Single-chip microcomputer h8/3062 series; h8/3062b series; h8/3062f-ztat series; h8/3064f-ztat series

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Table of Contents

Block Diagram of Channel 2: Figure 8.3 is a block diagram of channel 2

TCLKA to TCLKD

φ, φ/2, φ/4, φ/8

Timer counter 2 (16 bits)

GRA2, GRB2 :

General registers A2 and B2 (input capture/output compare registers)

(16 bits × 2)

Timer control register 2 (8 bits)

Timer I/O control register 2 (8 bits)

Clock selector

Figure 8.3 Block Diagram of Channel 2

Control logic

Module data bus