Module Standby Control Register H (Mstcrh) - Hitachi H8/3062 Hardware Manual

Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (CS
placed in the high-impedance state in software standby mode.
Bit 1
SSOE Description
0 In software standby mode, the address bus and bus control signals
are all high-impedance
1 In software standby mode, the address bus retains its output state and
bus control signals are fixed high
21.2.2

Module Standby Control Register H (MSTCRH)

MSTCRH is an 8-bit readable/writable register that controls output of the system clock (φ). It also
controls the module standby function, which places individual on-chip supporting modules in the
standby state. Module standby can be designated for the SCI0, SCI1.
Bit 7
PSTOP
Initial value 0
Read/Write R/W
φ clock stop
Enables or disables
output of the system clock
MSTCRH is initialized to H'78 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ φ φ φ Clock Stop (PSTOP): Enables or disables output of the system clock (φ).
Bit 7
PSTOP Description
0 System clock output is enabled
1 System clock output is disabled
to CS , AS, RD, HWR, and LWR) are kept as outputs or fixed high, or
0 7
6 5
— —
1 1
— —
Reserved bits
4 3 2
— — —
1 1 0
— — R/W
(Initial value)
1 0
MSTPH1 MSTPH0
0 0
R/W R/W
Module standby H1 to 0
These bits select modules
to be placed in standby
(Initial value)
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