Figure 22.3 Output Load Circuit - Hitachi H8/3062 Hardware Manual

Module Item
SCI Input Asyn-
clock chronous
cycle
Syn-
chronous
Input clock rise
time
Input clock fall
time
Input clock
pulse width
Transmit data
delay time
Receive data
setup time
(synchronous)
Receive Clock
data hold input
time (syn-
Clock
chronous)
output
Chip output pin
C
A
Symbol Min Max
t 4 —
Scyc
6 —
t 1.5 —
SCKr
t 1.5 —
SCKf
t 0.4 0.6
SCKW
t — 100
TXD
t 100 —
RXS
t 100 —
RXH
0 —
R
H

Figure 22.3 Output Load Circuit

Condition
B C
Min Max Min Max
4 — 4 —
6 — 6 —
1.5 — 1.5 —
1.5 — 1.5 —
0.4 0.6 0.4 0.6
— 100 — 100
100 — 100 —
100 — 100 —
0 — 0 —
R
L
C = 90 pF: ports 1 to 6, 8
C = 30 pF: ports 9, A, B, RESO
Ω
R = 2.4 k
L
Ω
R = 12 k
H
Input/output timing measurement levels
• Low: 0.8 V
• High: 2.0 V
Test
Unit Conditions
t Figure 22.30
cyc
t
cyc
t
cyc
t
cyc
t
Scyc
ns Figure 22.31
ns
ns
ns
669