A/D Control/Status Register (Adcsr); Table 14.3 Analog Input Channels And A/D Data Registers (Addra To Addrd) - Hitachi H8/3062 Hardware Manual

data register are reserved bits that are always read as 0. Table 14.3 indicates the pairings of analog
input channels and A/D data registers.
The CPU can always read and write the A/D data registers. The upper byte can be read directly,
but the lower byte is read through a temporary register (TEMP). For details see section 14.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.

Table 14.3 Analog Input Channels and A/D Data Registers (ADDRA to ADDRD)

Analog Input Channel
Group 0 Group 1
AN AN
0
AN AN
1
AN AN
2
AN AN
3
14.2.2

A/D Control/Status Register (ADCSR)

Bit
ADF
Initial value
R/(W) *
Read/Write
A/D end flag
Indicates end of A/D conversion
Note: * Only 0 can be written, to clear the flag.
A/D Data Register
ADDRA
4
ADDRB
5
ADDRC
6
ADDRD
7
7 6 5
ADIE ADST
0 0 0
R/W R/W
A/D start
Starts or stops A/D conversion
A/D interrupt enable
Enables and disables A/D end interrupts
4 3
SCAN CKS
0 0
R/W R/W
Clock select
Selects the A/D conversion time
Scan mode
Selects single mode or scan mode
2 1
CH2 CH1 CH0
0 0
R/W R/W R/W
Channel select 2 to 0
These bits select analog
input channels
0
0
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