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Notes on Use of Emulation in RAM:
1. Flash write enable (FWE) application and releasing
As in on-board program mode, care is required when applying and releasing FWE to prevent
erroneous programming or erasing. To prevent erroneous programming and erasing due to
program runaway during FWE application, in particular, the watchdog timer should be set
when the PSU, P, ESU, or E bit is set to 1 in FLMCR1, even while the emulation function is
being used. For details, see section 19.11, Flash Memory Programming and Erasing
Precautions.
2. NMI input disabling conditions
When the emulation function is used, NMI input is disabled when the P bit or E bit is set to 1
in FLMCR1, in the same way as with normal programming and erasing.
The P and E bits are cleared by a reset (including a watchdog timer reset), in standby mode,
when a high level is not being input to the FWE pin, or when the SWE bit in FLMCR1 is 0
while a high level is being input to the FWE pin.
3. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of
the value of RAM2 to RAM0 (emulation protection). In this state, setting the P or E bit in
FLMCR1 will not cause a transition to program mode or erase mode. When actually
programming or erasing a flash memory area, the RAMS bit should be cleared to 0.
4. A RAM area cannot be erased by execution of software in accordance with the erase algorithm
while flash memory emulation in RAM is being used.
5. Block area EB0 contains the vector table. When performing RAM emulation, the vector table
is needed in the overlap RAM.
19.9
NMI Input Disabling Conditions
All interrupts, including NMI input, should be disabled while flash memory is being programmed
or erased (while the P bit or E bit is set in FLMCR1), and while the boot program is executing in
boot mode *
1
, to give priority to the program or erase operation. There are three reasons for this:
1. NMI input during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the NMI exception handling sequence during programming or erasing, the vector would not
be read correctly *
3. If NMI input occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
For these reasons, in on-board programming mode alone there are conditions for disabling NMI
input, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All interrupt requests (exception handling and bus
release), including NMI, must therefore be restricted inside and outside the MCU during FWE
2
, possibly resulting in MCU runaway.
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