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3.4.6
Mode 6
This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available.
Mode 6 supports a maximum address space of 64 kbytes.
3.4.7
Mode 7
This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available.
Mode 7 supports a 1-Mbyte address space.
The versions with on-chip flash memory support an on-board programming mode in which the
flash memory can be programmed.
3.5
Pin Functions in Each Operating Mode
The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3
indicates their functions in each operating mode.
Table 3.3
Pin Functions in Each Mode
Port
Mode 1
Port 1
A
to A
7
0
Port 2
A
to A
15
8
Port 3
D
to D
15
8
*
1
Port 4
P4
to P4
7
0
Port 5
A
to A
19
16
Port A
PA
to PA
7
4
Notes: *1 Initial state. The bus mode can be switched by settings in ABWCR. These pins function
as P4
to P4
7
*2 Initial state. These pins become address output pins when the corresponding bits in the
data direction registers (P1DDR, P2DDR, P5DDR) are set to 1.
*3 Initial state. A
A
output by writing 0 in bits 7 to 5 of BRCR.
21
*4 Initial state. PA
BRCR.
Mode 2
Mode 3
A
to A
A
to A
7
0
7
0
A
to A
A
to A
15
8
15
8
D
to D
D
to D
15
8
15
8
*
1
D
to D
P4
to P4
7
0
7
A
to A
A
to A
19
16
19
16
PA
to PA
PA
to PA
7
4
6
*
3
A
20
in 8-bit bus mode, and as D
0
is always an address output pin. PA
20
to PA
are switched over to A
7
4
Mode 4
Mode 5
A
to A
P1
7
0
7
A
to A
P2
15
8
7
D
to D
D
15
8
15
*
1
*
1
D
to D
P4
0
7
0
7
A
to A
P5
19
16
3
,
PA
to PA
,
PA
4
6
4
7
*
3
A
20
to D
in 16-bit bus mode.
7
0
to PA
6
to A
23
20
Mode 6
*
2
to P1
P1
to P1
0
7
0
*
2
to P2
P2
to P2
0
7
0
to D
P3
to P3
8
7
0
*
1
to P4
P4
to P4
0
7
0
*
2
to P5
P5
to P5
0
3
0
*
4
to PA
PA
to PA
4
7
4
are switched over to A
4
output by writing 0 in bits 7 to 4 of
Mode 7
P1
to P1
7
0
P2
to P2
7
0
P3
to P3
7
0
P4
to P4
7
0
P5
to P5
3
0
PA
to PA
7
4
to
23
73
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